This invention relates to semiconductors, and is more specifically related to a process for planarization of a flash memory cell.
FIG. 1A and FIG. 1B are schematic, cross-sectional views of a conventional process for forming a floating gate. Referring to FIG. 1A, a polysilicon gate 112 is formed. Following to the formation, a silicon nitride layer 110 is deposited on the polysilicon gate 112. The silicon nitride layer 110 serves as a hard mask for the planarization of flash memory cells. However, the silicon nitride layer 110 has some drawbacks. First, the silicon nitride layer 110 needs to be removed with hot phosphorus acid in the following steps. The removal of the silicon nitride layer 110 is an additional step. Second, the silicon nitride layer 110 induces some defect issue and easily attracts mobile ions.
Still referring to FIG. 1A, a way to achieve planarization is to first deposit a high-density plasma oxide layer 104 over a substrate 100, wherein the silicon nitride layer 110 has the smallest thickness 120 of about 500 angstroms over the polysilicon gate 112. The HDP oxide layer 104 has the characteristic of having a sharp-pointed protuberance 108 on the silicon nitride layer 110 in a cross-sectional view. The sharp-pointed protuberance 108 is disadvantageous for the planarization and therefore needs to be removed.
Referring to FIG. 1B, to remove the silicon nitride layer 110 under the high-density plasma oxide layer 104 (FIG. 1A), a dipping process is performed to expose the silicon nitride layer 110. After the dipping process is performed, hot phosphorus acid is used to remove the silicon nitride layer 110. The nitride removal step takes a long time, about two hours. After that, several cleaning steps are necessary to ensure that no phosphorus acid remains on the substrate 100. Those cleaning steps also take time.
Taking a long time to remove the silicon nitride layer 110 means that the nitride layer 110 does have a great thickness. The thickness, for example, is about 1900 angstroms. Under the silicon nitride layer 110, the polysilicon pattern 112 (polysilicon gate) has a thickness of only about 1000 angstroms. In other words, the thickness of the silicon nitride layer 110 is almost double that of the polysilicon pattern 112. This thickness is a reason that a stress issue exists. In the subsequent thermal annealing step, the stress of the silicon nitride layer 110 is easily enhanced. The enhanced stress applies on the channel region 122 (in the surface of the substrate 100) under polysilicon pattern 112. With a transmission electronic microscope (TEM), some laceration traces due to the application are found in the channel region 122.
To sum up, the conventional process has the following drawbacks:
1. The dipping step, for partially removing the high-density plasma oxide layer, and the etching step for removing the silicon nitride layer, easily create defect issues.
2. Silicon nitride has an inherent stress problem, and increase the fabrication cost.
A purpose of the present invention is to provide a process in which planarization of a flash memory cell can be achieved. In this process, a first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In the etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.
According to a preferred embodiment of the present invention, the deposition and the etching of the high-density plasma oxide layer can be performed in the same chamber.
In another aspect, the present invention provides a process for forming a floating gate without formation of silicon nitride. The first polysilicon pattern having a top is formed over a substrate. A high-density plasma oxide layer covering the first polysilicon pattern is deposited in a first chamber. The high-density plasma oxide layer and the first polysilicon pattern are dry etched to partially remove the high-density plasma oxide layer and the first polysilicon pattern in a second chamber, the top of the first polysilicon pattern is therefore rounded. A second polysilicon pattern is formed over the substrate, wherein the second polysilicon pattern is wider than the first polysilicon pattern, and wherein the first and the second polysilicon patterns collectively serve as a floating gate.
The implementation of the present invention is a solution for a silicon nitride induced defect, and makes the formation of a floating gate more stable and controllable. Moreover, the process steps of the present invention are less than those of a conventional process.
On the other hand, according to the preferred embodiment of the present invention, a three dimensional floating gate having two polysilicon patterns is formed. This way of formation increases the gate coupling ratio (GCR) of the later-completed flash memory cell. Without the formation of a silicon nitride layer, there is no stress issue stemming from the silicon nitride layer. Moreover, hot phosphorus for removing silicon nitride is not necessary, thereby reducing the fabrication cost. Furthermore, without the step for removing silicon nitride, the process steps are simplified, and the fabrication cost is reduced. In the simplified process steps, no wet etching step is performed for removal of the high-density plasma oxide layer and the silicon nitride layer. This omission prevents the process from suffering defects and reliability issues.